Single-ended read Static Random Access Memory (SRAM) has been widely used in the industry because it can separate read and write operations to achieve lower minimum operating supply voltage (e.g., Vdd). Its large bit line leakage, however, could result in misread, especially in a long bit line scheme. Worst case current leakage to a bit line generally occurs when reading a cell storing a low while other cells are storing a high. When this happens, the current leakage causes a large voltage drop in the read bit line signal and thus can cause misread. Some approaches use a “keeper” to hold the reading state to avoid the misread. In many designs, however, the keeper is always on and thus can pull the logic level of the memory cell to be read in an undesirable direction.
Like reference symbols in the various drawings indicate like elements.